The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in the present disclosure and are not admitted to be prior art by inclusion in this section.
A cell in an NVM may store information by setting the voltage of the cell to a signal-level voltage of the cell. A signal-levels may refer to the voltage that the cell is set to by a “writer” of the storage device comprising the NVM. For example, the voltage of the cell may be set to one of two possible signal-levels by the writer. If the cell only comprises two possible signal-levels, then the one-bit value of “0” may be stored in the cell by setting the cell to a first signal-level, and the one-bit value of “1” may be stored in the cell by setting the cell to a second signal-level. Similarly, if the cell of NVM is capable of storing information at one of four signal-levels, i.e., the cell is a cell of MLC NVM, then the first, second, third, and fourth signal-levels may respectively represent the two-bit values “00,” “01,” “10,” and “11.”